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8.6 Optional Bus Configuration
The MPC750 supports an optional bus configuration that is selected by the assertion or
negation of the DRTRY signal during the negation of the HRESET signal. The operation
and selection of the optional bus configuration is described in the following sections.
8.6.1 No-DRTRY Mode
The MPC750 supports an optional mode to disable the use of the data retry function
provided through the DRTRY signal. The no-DRTRY mode allows the forwarding of data
during load operations to the internal CPU one bus cycle sooner than in the normal bus
protocol.
The 60x bus protocol specifies that, during load operations, the memory system normally
has the capability to cancel data that was read by the master on the bus cycle after TAwas
asserted. In the MPC750 implementation, this late cancellation protocol requires the
MPC750 to hold any loaded data at the bus interface for one additional bus clock to verify
that the data is valid before forwarding it to the internal CPU. For systems that do not
implement the DRTRY function, the MPC750 provides an optional no-DRTRY mode that
eliminates this one-cycle stall during all load operations, and allows for the forwarding of
data to the internal CPU immediately when T A is recognized.
When the MPC750 is in the no-DRTRY mode, data can no longer be cancelled the cycle
after it is acknowledged by an assertion ofTA. Data is immediately forwarded to the CPU
internally, and any attempt at late cancellation by the system may cause improper operation
by the MPC750.
When the MPC750 is following normal bus protocol, data may be cancelled the bus cycle
after
fA
by either of two means-late cancellation by DRTRY, or late cancellation by
ARTRY. When no-DRTRY mode is selected, both cancellation cases must be disallowed
in the system design for the bus protocol.
When no-DRTRY mode is selected for the MPC750, the system must ensure that DRTRY
is not asserted to the MPC750. If it is asserted, it may cause improper operation of the bus
interface. The system must also ensure that an assertion of ARTRY by a snooping device
must occur before or coincident with the first assertion of T A to the MPC750, but not on
the cycle after the first assertion of T A.
Other than the inability to cancel data that was read by the master on the bus cycle after T A
was asserted, the bus protocol for the MPC750 is identical to that for the basic transfer bus
protocols described in this chapter.
The MPC750 selects the desired DRTRY mode at startup by sampling the state of the
DRTRY signal itself at the negation of the HRESET signal. If the DRTRY signal is negated
at the negation of HRESET, normal operation is selected. If the DRTRY signal is asserted
at the negation of HRESET, no-DRTRY mode is selected.
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MPC750 RISC Microprocessor User's Manual
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