Table of Contents
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xviii
ILLUSTRATIONS
Title
Page
Number
Primary Page Table Search ................................................................................ 5-32
Secondary Page Table Search Flow ................................................................... 5-33
Pipelined Execution Unit ..................................................................................... 6-4
SuperscalarlPipeline Diagram .............................................................................. 6-5
MPC750 Microprocessor Pipeline Stages ........................................................... 6-7
Instruction Flow Diagram .................................................................................. 6-10
Instruction Timing-Cache Hit ......................................................................... 6-12
Instruction Timing-Cache Miss ....................................................................... 6-15
Branch Folding ................................................................................................... 6-19
Removal of Fall-Through Branch Instruction .................................................... 6-19
Branch Completion ............................................................................................ 6-20
Branch Instruction Timing ................................................................................. 6-23
MPC750 Signal Groups ....................................................................................... 7-3
MPC750 Microprocessor Block Diagram ........................................................... 8-3
Timing Diagram Legend ...................................................................................... 8-6
Overlapping Tenures on the MPC750 Bus for a Single-Beat Transfer ............... 8-7
Address Bus Arbitration .................................................................................... 8-10
Address Bus Arbitration Showing Bus Parking ................................................. 8-11
Address Bus Transfer ......................................................................................... 8-13
Snooped Address Cycle withARTRY ............................................................... 8-19
Data Bus Arbitration .......................................................................................... 8-20
Normal Single-Beat Read Termination ............................................................. 8-23
Normal Single-Beat Write Termination ............................................................. 8-23
Normal Burst Transaction .................................................................................. 8-24
Termination with DRTRY .................................................................................. 8-25
Read Burst with TA Wait States and DRTRY ................................................... 8-25
MEl Cache Coherency Protocol-State Diagram (WIM = 001) ....................... 8-27
Fastest Single-Beat Reads .................................................................................. 8-28
Fastest Single-Beat Writes ................................................................................. 8-29
Single-Beat Reads Showing Data-Delay Controls ............................................ 8-30
Single-Beat Writes Showing Data Delay Controls ............................................ 8-31
Burst Transfers with Data Delay Controls ......................................................... 8-32
Use of Transfer Error Acknowledge (TEA) ...................................................... 8-33
IEEE 1149.1a-1993 Compliant Boundary Scan Interface ................................. 8-37
Data Bus Write Only Transaction ...................................................................... 8-38
Typical1-Mbyte L2 Cache Configuration ........................................................... 9-2
Burst Read-Write-Read L2 Cache Access (Flow-Through) .............................. 9-10
Burst Read-Modify-Write L2 Cache Access (Flow-Through) .......................... 9-10
Burst Read-Write-Write L2 Cache Access (Flow-Through) ............................. 9-11
Burst Read-Write-Read L2 Cache Access (Pipelined) ...................................... 9-11
Burst Read-Modify-Write L2 Cache Access (Pipelined) .................................. 9-12
Burst Read-Write-Write L2 Cache Access (Pipelined) ..................................... 9-12
Burst Read-Write-Read L2 Cache Access (Late-Write SRAM) ....................... 9-13
MPC750 RISC Microprocessor User's Manual
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