Table of Contents
Advertisement
Within one cycle, the instruction cache provides up to four instructions to the instruction
queue. The instruction cache can be invalidated entirely or on a cache-block basis. The
instruction cache can be disabled and invalidated by clearing HIDO[ICE] and setting
HIDO[ICFI]. The instruction cache can be locked by setting HIDO[ILOCK]. The instruction
cache supports only the valid/invalid states.
The MPC750 also implements a 64-entry (16-set, four-way set-associative) branch target
instruction cache (BTIC). The BTIC is a cache of branch instructions that have been
encountered in branch/loop code sequences.
If
the target instruction is in the BTIC, it is
fetched into the instruction queue a cycle sooner than it can be made available from the
instruction cache. Typically the BTIC contains the first two instructions in the target stream.
The BTIC can be disabled and invalidated through software.
For more information and timing examples showing cache hit and cache miss latencies, see
Section 6.3.2, "Instruction Fetch Timing."
1.2.5 L2 Cache Implementation (Not Supported in the MPC740)
The L2 cache is a unified cache that receives memory requests from both the Ll instruction
and data caches independently. The L2 cache is implemented with an on-chip, two-way,
set-associative tag memory, and with external, synchronous SRAMs for data storage. The
external SRAMs are accessed through a dedicated L2 cache port that supports a single bank
of up to 1 Mbyte of synchronous SRAMs. The L2 cache normally operates in write-back
mode and supports system cache coherency through snooping.
Depending on its size, the L2 cache is organized into 64- or 128-byte lines, which in tum
are subdivided into 32-byte sectors (blocks), the unit at which cache coherency is
maintained.
The L2 cache controller contains the L2 cache control register (L2CR), which includes bits
for enabling parity checking, setting the L2-to-processor clock ratio, and identifying the
type of RAM used for the L2 cache implementation. The L2 cache controller also manages
the L2 cache tag array, two-way set-associative with 4K tags per way. Each sector (32-byte
cache block) has its own valid and modified status bits.
Requests from the Ll cache generally result from instruction misses, data load or store
misses, write-through operations, or cache management instructions. Requests from the Ll
cache are looked up in the L2 tags and serviced by the L2 cache if they hit; they are
forwarded to the bus interface if they miss.
The L2 cache can accept multiple, simultaneous accesses. The Ll instruction cache can
request an instruction at the same time that the Ll data cache is requesting one load and two
store operations. The L2 cache also services snoop requests from the bus. If there are
multiple pending requests to the L2 cache, snoop requests have highest priority. The next
priority consists of load and store requests from the Ll data cache. The next priority
consists of instruction fetch requests from the L 1 instruction cache.
1-14
MPC750 RISC Microprocessor User's Manual
Advertisement
Table of Contents
