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Table 4-10. Trace Exception-SRR1 Settings
Register
Setting
SRRl
0-2
010
3
Set for a load instruction, otherwise cleared
4
Set for a store instruction, otherwise cleared
5-9
Cleared
10
Set for Iswx or stswx, otherwise cleared
11
Set for mtspr to SOR1, EAR, HIOO, PIR, IBATs, OBATs, SRs
12
Set for taken branch, otherwise cleared
13-15 Cleared
16-31 MSR[16-31]
Implementation Note-The MPC750 processor diverges from the PowerPC architecture
in that it does not take trace exceptions on the isync instruction.
When a trace exception is taken, instruction fetching resumes as offset OxOODOO from the
base address indicated by MSR[IP).
4.5.12 Floating-Point Assist Exception (OxOOEOO)
The optional floating-point assist exception defined by the PowerPC architecture is not
implemented in the MPC750.
4.5.13 Performance Monitor Interrupt (OxOOFOO)
The MPC750 microprocessor provides a performance monitor facility to monitor and count
predefined events such as processor clocks, misses in either the instruction cache or the data
cache, instructions dispatched to a particular execution unit, mispredicted branches, and
other occurrences. The count of such events can be used to trigger the performance monitor
exception. The performance monitor facility is not defined by the PowerPC architecture.
The performance monitor can be used for the following:
•
To increase system performance with efficient software, especially in a
multiprocessing system. Memory hierarchy behavior must be monitored and studied
to develop algorithms that schedule tasks (and perhaps partition them) and that
structure and distribute data optimally.
• To help system developers bring up and debug their systems.
The performance monitor uses the following SPRs:
• The performance monitor counter registers (PMCI-PMC4) are used to record the
number of times a certain event has occurred. UPMCI-UPMC4 provide user-level
read access to these registers.
• The monitor mode control registers (MMCRO-MMCRl) are used to enable various
performance monitor interrupt functions. UMMCRO-UMMCRI provide user-level
read access to these registers.
4-20
MPC750 RISC Microprocessor User's Manual
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