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Figure 6-1 represents a generic pipelined execution unit.
Stage 1
Stage 2
Stage 3
r-------~Ir-------_.._------~I
Clock 0
I I
Instruction A
III
I I
I
I
Clock
1
:
I:
Clock
2
I
I.-----~~ r~--~~~~----~
I~------~
~
______
~L-
_ _ _ _ _ _
~
Ir-----~~ ~~--~_.~~-----.
I
Instruction D
L -_ _ _ _ _ _
~
~
_ _ _ _ _ _
~L-
_ _ _ _ _ _
~
Clock 3
Figure 6-1. Pipelined Execution Unit
The entire path that instructions take through the fetch, decode/dispatch, execute, complete,
and write-back stages is considered the MPC750's master pipeline, and two of the
MPC750's execution units (the FPU and LSU) are also multiple-stage pipelines.
The MPC750 contains the following execution units that operate independently and in
parallel:
• Branch processing unit (BPU)
• Integer unit 1 (IUl)--executes all integer instructions
•
Integer unit 2 (IU2)--executes all integer instructions except multiplies and divides
•
64-bit floating-point unit (FPU)
• Load/store unit (LSU)
• System register unit (SRU)
The MPC750 can retire two instructions on every clock cycle. In general, the MPC750
processes instructions in four stages-fetch, decode/dispatch, execute, and complete as
shown in Figure 6-2. Note that the example of a pipelined execution unit in Figure 6-1 is
similar to the three-stage FPU pipeline in Figure 6-2.
6-4
MPC750 RISC Microprocessor User's Manual
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