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cache when a hit occurs. Cacheable single-beat read and writes occur when address
translation is disabled (invoking the use of the default WIMG bits (ObOOll)), or when
address translation is enabled and accesses are marked as cacheable through the page table
entries or the BATs, and the L1 data cache is disabled or locked. When the L2 cache has
been initialized and the L1 cache has been disabled or locked, load or store instructions then
bypass the L1 cache and hit in the L2 cache directly. When L2CR[TS] is set, cacheable
single-beat writes are inhibited from accessing the 60x bus interface after an L2 cache miss.
During L2 cache testing, the performance monitor can be used to count L2 cache hits and
misses, thereby providing a numerical signature for test routines and a way to verify proper
L2 cache operation.
9.1.5.2 L2 Cache Testing
A typical test for verifying the proper operation of the MPC750's L2 cache memory
(external SRAM and tag) would perform the following steps:
9-8
•
Initialize the L2 test sequence by disabling address translation to invoke the default
WIMG setting (ObOOll). Set L2CR[DO] and L2CR[TS] and perform a global
invalidation of the Ll data cache and the L2 cache. The Ll instruction cache can
remain enabled to improve execution efficiency.
•
Test the L2 cache external SRAM by enabling the L1 data cache and executing a
sequence of
debz, stw, and debf
instructions to initialize the L2 cache with a desired
range of consecutive addresses and with cache data consisting of zeros. Once the L2
cache holds a sequential range of addresses, disable the Ll data cache and execute
a series of single-beat load and store operations employing a variety of bit patterns
to test for stuck bits and pattern sensitivities in the L2 cache SRAM. The
performance monitor can be used to verify whether the number of L2 cache hits or
misses corresponds to the tests performed.
•
Test the L2 cache tag memory by enabling the L 1 data cache and executing a
sequence of
debz, stw, and debf
instructions to initialize the L2 cache with a wide
range of addresses and cache data. Once the L2 cache is populated with a known
range of addresses and data, disable the Ll data cache and execute a series of store
operations to addresses not previously in the L2 cache. These store operations
should miss in every case. Note that setting the L2CR[TS] inhibits L2 cache misses
from being forwarded to the 60x bus interface, thereby avoiding the potential for bus
errors due to addressing hardware or nonexistent memory. The L2 cache then can be
further verified by reading the previously loaded addresses and observing whether
all the tags hit, and that the associated data compares correctly. The performance
monitor can also be used to verify whether the proper number of L2 cache hits and
misses correspond to the test operations performed.
•
The entire L2 cache can be tested by clearing L2CR[DO] and L2CR[TS], restoring
the Ll and L2 caches to their normal operational state, and executing a
comprehensive test program designed to exercis.e all the caches. The test program
should include operations that cause L2 hit, reload, and castout activity that can be
subsequently verified through the performance monitor.
MPC750 RISC Microprocessor User's Manual
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