Direct-Store Accesses - Motorola MPC750 User Manual

Typically, memory accesses are weakly ordered to maximize the efficiency of the bus
without sacrificing coherency of the data. The MPC750 allows load operations to bypass
store operations (except when a dependency exists). In addition, the MPC750 can be
configured to reorder high-priority store operations ahead of lower-priority store
operations. Because the processor can dynamically optimize run-time ordering of
load/store traffic, overall performance is improved.
Note that the synchronize (sync) and enforce in-order execution of 10 (eieio) instructions
can be used to enforce strong ordering.
The following sections describe how the MPC750 interface operates, providing detailed
timing diagrams that illustrate how the signals interact. A collection of more general timing
diagrams are included as examples of typical bus operations.
Figure 8-2 is a legend of the conventions used in the timing diagrams.
This is a synchronous interface-all MPC750 input signals are sampled and output signals
are driven on the rising edge of the bus clock cycle (see the MPC750 hardware
specifications for exact timing information).
8.1.4 Direct-Store Accesses
The MPC750 does not support the extended transfer protocol for accesses to the
direct-store storage space. The transfer protocol used for any given access is selected by the
T bit in the MMU segment registers; if the T bit is set, the memory access is a direct-store
access. An attempt to access instructions or data in a direct-store segment will result in the
MPC750 taking an lSI or DSI exception.
Chapter 8. System Interface Operation
8-5