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8.3.2.3 Burst Ordering During Data Transfers
During burst data transfer operations, 32 bytes of data (one cache line) are transferred to or
from the cache in order. Burst write transfers are always performed zero double word first,
but since burst reads are performed critical double word first, a burst read transfer may not
start with the first double word of the cache line, and the cache line fill may wrap around
the end of the cache line.
Table 8-2 describes the data bus burst ordering.
Table 8-2. Burst Ordering
For Starting Address:
Data Transfer
A[27-28]
=
00
A[27-28]
=
01
A[27-28]
=
10
A[27-28]
=
11
First data beat
DWO
DW1
DW2
DW3
Second data beat
DW1
DW2
DW3
DWO
Third data beat
DW2
DW3
DWO
DW1
Fourth data beat
DW3
DWO
DW1
DW2
Note: A[29-31) are always ObOOO for burst transfers by the MPC750.
8.3.2.4 Effect of Alignment in Data Transfers
Table 8-3 lists the aligned transfers that can occur on the MPC750 bus. These are transfers
in which the data is aligned to an address that is an integral multiple of the size of the data.
For example, Table 8-3 shows that I-byte data is always aligned; however, for a 4-byte
word to be aligned, it must be oriented on an address that is a multiple of 4.
Table 8-3. Aligned Data Transfers
Data Bus Byte Lane(s)
Transfer Size
TSIZO
TSIZ1
TSIZ2
A[29-31]
0
1
2
3
4
5
6
7
Byte
0
0
1
000
oJ
-
-
-
-
-
-
-
0
0
1
001
-
oJ
-
-
-
-
-
-
0
0
1
010
-
-
oJ
-
-
-
-
-
0
0
1
011
-
-
-
oJ
-
-
-
-
0
0
1
100
-
-
-
-
oJ
-
-
-
0
0
1
101
-
-
-
-
-
...j
-
-
0
0
1
110
-
-
-
-
-
-
oJ
-
0
0
1
111
-
-
-
-
-
-
-
oJ
Chapter 8. System Interface Operation
8-15
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