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9.1.4 L2 Cache Global Invalidation
The L2 cache supports a global invalidation function in which all bits of the L2 tags (tag
data bits, tag status bits, and LRU bit) are cleared. It is performed by an on-chip hardware
state machine that sequentially cycles through the L2 tags. The global invalidation function
is controlled through L2CR[L2I], and it must be performed only while the L2 cache is
disabled. The MPC750 can continue operation during a global invalidation provided the L2
cache has been properly disabled before the global invalidation operation starts.
The sequence for performing a global invalidation of the L2 cache is as follows:
•
Execute a sync instruction to finish any pending store operations in the load/store
unit, disable the L2 cache by clearing L2CR[L2E], and execute an additional sync
instruction after disabling the L2 cache to ensure that any pending operations in the
L2 cache unit have completed.
•
Initiate the global invalidation operation by setting the L2CR[L2I] bit to 1.
•
Monitor the L2CR[L2IP] bit to determine when the global invalidation operation is
completed (indicated by the clearing of L2CR[L2IP]). The global invalidation
requires approximately 32K core clock cycles to complete.
•
After detecting the clearing of L2CR[L2IP], clear L2CR[L2I] and re-enable the L2
cache for normal operation by setting L2CR[L2E].
9.1.5 L2 Cache Test Features and Methods
In the course of system power-up, testing may be required to verify the proper operation of
the L2 tag memory, external SRAM, and overall L2 cache system. The following sections
describe the MPC750's features and methods for testing the L2 cache. The L2 cache
address space should be marked as guarded (G
=
1)
so spurious load operations are not
forwarded to the 60x bus interface before branch resolution during L2 cache testing.
9.1.5.1 L2CR Support for L2 Cache Testing
L2CR[DO] and L2CR[TS] support the testing of the L2 cache. L2CR[DO] prevents
instructions from being cached in the L2. This allows the L1 instruction cache to remain
enabled during the testing process without having LI instructioh misses affect the contents
of the L2 cache and allows all L2 cache activity to be controlled by program-specified load
and store operations.
L2CR[TS] is used with the debf and debst instructions to push data into the L2 cache.
When L2CR[TS] is set, and the L1 data cache is enabled, an instruction loop containing a
debf instruction can be used to store any address or data pattern to the L2 cache.
Additionally, 60x bus broadcasting is inhibited when a debz instruction is executed. This
allows the use of a debz instruction to clear an L1 cache block, followed by a debf
instruction to push the cache block into the L2 cache and invalidate the L1 cache block.
When the L2 cache is enabled, cacheable single-beat read operations are allowed to hit in
the L2 cache and cacheable write operations are allowed to modify the contents of the L2
Chapter 9. L2 Cache Interface Operation
9-7
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