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6.4.4 Effect of Floating-Point Exceptions on Performance
For the fastest and most predictable floating-point performance, all exceptions should be
disabled in the FPSCR and MSR.
6.4.5 Load/Store Unit Execution Timing
The execution of most load and store instructions is pipelined. The LSD has two pipeline
stages. The first is for effective address calculation and MMD translation and the second is
for accessing data in the cache. Load and store instructions have a two-cycle latency and
one-cycle throughput.
If operands are misaligned, additional latency may be required either for an alignment
exception to be taken or for additional bus accesses. Load instructions that miss in the cache
block subsequent cache accesses during the cache line refill. Table 6-8 gives load and store
instruction execution latencies.
6.4.6 Effect of Operand Placement on Performance
The PowerPC YEA states that the placement (location and alignment) of operands in
memory may affect the relative performance of memory accesses, and in some cases affect
it significantly. The effects memory operand placement has on performance are shown in
Table 6-1.
The best performance is guaranteed if memory operands are aligned on natural boundaries.
For the best performance across the widest range of implementations, the programmer
should assume the performance model described in Chapter 3, "Operand Conventions," in
The Programming Environments Manual.
The effect of misalignment on memory access latency is the same for big- and little-endian
addressing modes except for multiple and string operations that cause an alignment
exception in little-endian mode.
Chapter 6. Instruction Timing
6-25
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