Transfer Error Acknowledge (Tea)-Input - Motorola MPC750 User Manual

for one bus clock cycle and then negate it to advance the burst
transfer to the next beat and insert wait states during the next beat.
7.2.8.2 Data Retry (DRTRV)-Input
Following are the state meaning and timing comments for the DRTRY signal.
State Meaning
Asserted-Indicates that the MPC750 must invalidate the data from
the previous read operation.
Negated-Indicates that data presented with TA on the previous read
operation is valid. Note that DRTRY is ignored for write
transactions.
Timing Comments
Assertion-Must occur during the bus clock cycle immediately after
TA is asserted if a retry is required. The DRTRY signal may be held
asserted for multiple bus clock cycles. When DRTRY is negated,
data must have been valid on the previous clock with TA asserted.
Negation-Must occur during the bus clock cycle after a valid data
beat. This may occur several cycles after DBB is negated, effectively
extending the data bus tenure.
Start-up-The DRTRY signal is sampled at the negation of
HRESET; if DRTRY is asserted, no-DRTRY mode is selected. If
DRTRY is negated at start-up, DRTRY is enabled.
7.2.8.3 Transfer Error Acknowledge (TEA)-Input
Following are the state meaning and timing comments for the TEA signal.
State Meaning
Asserted-Indicates that a bus error occurred. Causes a machine
check exception (and possibly causes the processor to enter
checkstop state if machine check enable bit is cleared
(MSR[ME]
=
0)). For more information, see Section 4.5.2.2,
"Checks top State (MSR[ME]
=
0)." Assertion terminates the current
transaction; that is, assertion of TA and DRTRY are ignored. The
assertion of TEA causes the negation/high impedance ofDBB in the
next clock cycle. However, data entering the GPR or the cache are
not invalidated. (Note that the term 'exception' is also referred to as
'interrupt' in the architecture specification.)
Negated-Indicates that no bus error was detected.
Timing Comments
Assertion-May be asserted while DBB is asserted, and the cycle
after TA during a read operation. TEA should be asserted for one
cycle only.
Negation-TEA must be negated no later than the negation of DBB.
7-20 MPC750 RISC Microprocessor User's Manual