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Branch instructions are identified by the fetcher, and forwarded to the BPU directly,
bypassing the dispatch queue. If the branch is unconditional or if the specified conditions
are already known, the branch can be resolved immediately. That is, the branch direction is
known and instruction fetching can continue from the correct location. Otherwise, the
branch direction must be predicted. The MPC750 offers several resources to aid in quick
resolution of branch instructions and for improving the accuracy of branch predictions.
These include the following:
•
Branch target instruction cache-The 64-entry (four-way-associative) branch target
instruction cache (BTIC) holds branch target instructions so when a branch is
encountered in a repeated loop, usually the first two instructions in the target stream
can be fetched into the instruction queue on the next clock cycle. The BTIC can be
disabled and invalidated through bits in HIDO.
•
Dynamic branch prediction-The 512-entry branch history table (BHT) is
implemented with two bits per entry for four degrees of prediction-not-taken,
strongly not-taken, taken, strongly taken. Whether a branch instruction is taken or
not-taken can change the strength of the next prediction. This dynamic branch
prediction is not defined by the PowerPC architecture.
To reduce aliasing, only predicted branches update the BHT entries. Dynamic
branch prediction is enabled by setting HIDO[BHT]; otherwise, static branch
prediction is used.
•
Static branch prediction-Static branch prediction is defined by the PowerPC
architecture and involves encoding the branch instructions. See Section 6.4.1.3.1,
"Static Branch Prediction."
Branch instructions that do not update the LR or CTR are removed from the instruction
stream either by branch folding or removal of fall-through branch instructions, as described
in Section 6.4.1.1, "Branch Folding and Removal of Fall-Through Branch Instructions."
Branch instructions that update the LR or CTR are treated as if they require dispatch (even
through they are not issued to an execution unit in the process). They are assigned a position
in the completion queue to ensure that the CTR and LR are updated sequentially.
All other instructions are issued from the IQO and IQl. The dispatch rate depends upon the
availability of resources such as the execution units, rename registers, and completion
queue entries, and upon the serializing behavior of some instructions. Instructions are
dispatched in program order; an instruction in IQI cannot be dispatched ahead of one in
IQO.
Chapter 6. Instruction Timing
6-9
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