Table of Contents
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L
LlIL2 interface operation, see Cache
L2ADDRn (L2 address) signals, 7-25
L2CE (L2 chip enable) signals, 7-26
L2CLK OUTA (L2 clock out A) signal, 7-27
L2CLK_OUTB (L2 clock out B) signal, 7-27
L2CR (L2 cache control register), 2-24, 9-4
L2DATAn (L2 data) signals, 7-25
L2DPn (L2 data parity) signals, 7-26
L2SYNC IN (L2 sync in) signal, 7-28
L2SYNC_OUT (L2 sync out) signal, 7-27
L2WE (L2 write enable) signal, 7-27
L2ZZ (L210w-power mode enable) signal, 7-28
Latency, 8-21
Latency
definition, 6-2
load/store instructions, 6-36
Load/store
address generation, 2-46
byte reverse instructions, 2-49, A-23
execution timing, 6-25
floating-point load instructions, 2-51, A-24
floating-point move instructions, 2-44, A-25
floating-point store instructions, 2-52, A-25
handling misalignment, 2-45
integer load instructions, 2-46, A-22
integer store instructions, 2-47, A-23
latency, load/store instructions, 6-36
load/store multiple instructions, 2-49, A-23
memory synchronization instructions, A-24
string instructions, 2-50, A-24
Logical address translation, 5-1
Logical instructions, integer, A-18
Lookaside buffer management instructions, A-28
LR (link register), 2-4
lwarx/stwcx. support, 8-36
M
Machine check exception, 4-14
MCP (machine check interrupt) signal, 7-21
MEl protocol
hardware considerations, 3-9
read operations, 3-23
state transitions, 3-32
Memory accesses, 8-4
Memory coherency bit (M bit)
cache interactions, 3-6
timing considerations, 6-27
Memory control instructions
description, 2-62, 2-66
segment register manipulation, A-28
SLB management, A-28
Index
INDEX
Memory management unit
address translation flow, 5-12
address translation mechanisms, 5-9, 5-12
block address translation, 5-9, 5-12, 5-21
block diagrams
32-bit implementations, 5-6
DMMU, 5-8
IMMU, 5-7
exceptions summary, 5-16
features summary, 5-3
implementation-specific features, 5-2
instructions and registers, 5-18
memory protection, 5-11
overview, 1-12, 5-2
page address translation, 5-9, 5-12, 5-28
page history status, 5-12, 5-21-5-25
real addressing mode, 5-12, 5-20
segment model, 5-21
Memory synchronization instructions, 2-59, 2-61,
A-24
Misalignment
misaligned accesses, 2-29
misaligned data transfer, 8-17
MMCRn
(monitor mode control registers), 2-14,
4-20,11-3
MSR (machine state register)
bit settings, 4-8
FEOIFEI bits, 4-10
IP bit, 4-13
PM bit, 2-4
RI bit, 4-11
settings due to exception, 4-12
Multiple-precision shifts, 2-41
Multiply-add instructions, A-20
N
No-DRTRY mode, 8-34
o
OEA
exception mechanism, 4-1
memory management specifications, 5-1
registers, 2-4
Operand conventions, 2-28
Operand placement and performance, 6-25
Operating P!1vironment architecture (OEA), xxviii
1-21
'
Operations
bus operations caused by cache control
instructions, 3-24
cache operations, 3-1
data cache block push, 3-22
enveloped high-priority cache block push, 3-22
Index-5
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