Quiescent Request (Qreq)-Output; Quiescent Acknowledge (Qack)-Input; Reservation (Rsrv)-Output; Time Base Enable (Tben)-Input - Motorola MPC750 User Manual

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7.2.9.7.1 Quiescent Request (QREQ)-Output
Following are the state meaning and timing comments for QREQ.
State Meaning
Asserted-Indicates that the MPC750 is requesting all bus activity
normally required to be snooped to terminate or to pause so the
MPC750 may enter a quiescent (low power) state. When the
MPC750 has entered a quiescent state, it no longer snoops bus
activity.
Negated-Indicates that the MPC750 is not making a request to
enter the quiescent state.
Timing Comments AssertionlNegation-May occur on any cycle. QREQ will remain
asserted for the duration of the quiescent state.
7.2.9.7.2 Quiescent Acknowledge (QACK)-Input
Following are the state meaning and timing comments for the QACK signal.
State Meaning
Asserted-Indicates that all bus activity that requires snooping has
terminated or paused, and that the MPC750may enter the quiescent
(or low power) state.
Negated-Indicates that the MPC750 may not enter a quiescent
state, and must continue snooping the bus.
Timing Comments AssertionlNegation-May occur on any cycle following the
assertion of QREQ, and must be held asserted for at least one bus
clock cycle.
7.2.9.7.3 Reservation (RSRV)-Output
Following are the state meaning and timing comments for RSRV.
State Meaning
Asserted/Negated-Represents the state of the reservation
coherency bit in the reservation address register that is used by the
lwarx and stwcx. instructions. See Section 8.8.1, "Support for the
lwarxlstwcx. Instruction Pair."
Timing Comments AssertionlNegation-Occurs synchronously with respect to bus
clock cycles. The execution of an lwarx instruction sets the internal
reservation condition.
7.2.9.7.4 Time Base Enable (TBEN)-Input
Following are the state meaning and timing comments for the TBEN signal.
State Meaning
Asserted-Indicates that the time base should continue clocking.
This input is essentially a count enable control for the time base
counter.
Negated-Indicates the time base should stop clocking.
Timing Comments AssertionlNegation-May occur on any cycle.
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MPC750 RISC Microprocessor User's Manual

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