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Chapter 7
Signal Descriptions
This chapter describes the MPC750 microprocessor's external signals. It contains a concise
description of individual signals, showing behavior when the signal is asserted and negated
and when the signal is an input and an output.
NOTE
A bar over a signal name indicates that the signal is active
low-for example, ARTRY (address retry) and TS (transfer
start). Active-low signals are referred to as asserted (active)
when they are low and negated when they are high. Signals that
are not active low, such as AP[O-3] (address bus parity signals)
and
TT[~]
(transfer type signals) are referred to as asserted
when they are high and negated when they are low.
The MPC750 signals are grouped as follows:
• Address arbitration-The MPC750 uses these signals to arbitrate for address bus
mastership.
•
Address transfer start-These signals indicate that a bus master has begun a
transaction on the address bus.
•
Address transfer-These signals include the address bus and address parity signals.
They are used to transfer the address and to ensure the integrity of the transfer.
•
Transfer attribute-These signals provide information about the type of transfer,
such as the transfer size and whether the transaction is bursted, write-through, or
cache-inhibited.
•
Address transfer termination-These signals are used to acknowledge the end of the
address phase of the transaction. They also indicate whether a condition exists that
requires the address phase to be repeated.
•
Data arbitration-The MPC750 uses these signals to arbitrate for data bus
mastership.
• Data transfer-These signals, which consist of the data bus and data parity, are used
to transfer the data and to ensure the integrity of the transfer.
Chapter 7. Signal Descriptions
7-1
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