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Chapter 11
Performance Monitor
The performance monitor facility provides the ability to monitor and count predefined
events such as processor clocks, misses in the instruction cache, data cache, or L2 cache,
types of instructions dispatched, mispredicted branches, and other occurrences. The count
of such events (which may be an approximation) can be used to trigger the performance
monitor exception. The performance monitor facility is not defined by the PowerPC
architecture.
The performance monitor can be used for the following:
•
To increase system performance with efficient software, especially in a
multiprocessing system. Memory hierarchy behavior may be monitored and studied
in order to develop algorithms that schedule tasks (and perhaps partition them) and
that structure and distribute data optimally.
•
To improve processor architecture, the detailed behavior of the MPC750's structure
must be known and understood in many software environments. Some environments
may not be easily characterized by a benchmark or trace.
•
To help system developers bring up and debug their systems.
The performance monitor uses the following MPC750-specific special-purpose registers
(SPRs):
•
The performance monitor counter registers (PMCI-PMC4) are used to record the
number oftimes a certain event has occurred. UPMCI-UPMC4 provide user-level
read access to these registers.
•
The monitor mode control registers (MMCRO-MMCRl) are used to enable various
performance monitor interrupt functions and select events to count.
UMMCRO-UMMCRl provide user-level read access to these registers.
•
The sampled instruction address register (SIA) contains the effective address of an
instruction executing at or around the time that the processor signals the
performance monitor interrupt condition. USIA provides user-level read access to
the SIA.
Chapter 11. Performance Monitor
11-1
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