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6.4.1.3 Branch Prediction and Resolution
The MPC750 supports the following two types of branch prediction:
•
Static branch prediction-This is defined by the PowerPC architecture as part of the
encoding of branch instructions.
•
Dynamic branch prediction-This is a processor-specific mechanism implemented
in hardware (in particular the branch history table, or BHT) that monitors branch
instruction behavior and maintains a record from which the next occurrence of the
branch instruction is predicted.
When a conditional branch cannot be resolved due to a CR data dependency, the BPU
predicts whether it will be taken, and instruction fetching proceeds down the predicted path.
If
the branch prediction resolves as incorrect, the instruction queue and all subsequently
executed instructions are purged, instructions executed prior to the predicted branch are
allowed to complete, and instruction fetching resumes down the correct path.
The MPC750 executes through two levels of prediction. Instructions from the first
unresolved branch can execute, but they cannot complete until the branch is resolved. If a
second branch instruction is encountered in the predicted instruction stream, it can be
predicted and instructions can be fetched, but not executed, from the second branch. No
action can be taken for a third branch instruction until at least one of the two previous
branch instructions is resolved.
The number of instructions that can be executed after the issue of a predicted branch
instruction is limited by the fact that no instruction executed after a predicted branch may
actually update the register files or memory until the branch is completed. That is,
instructions may be issued and executed, but cannot reach the write-back stage in the
completion unit. When an instruction following a predicted branch completes execution, it
does not write back its results to the architected registers, instead, it stalls in the completion
queue. Of course, when the completion queue is full, no additional instructions can be
dispatched, even if an execution unit is idle.
In the case of a misprediction, the MPC750 can easily redirect its machine state because the
programming model has not been updated. When a branch is rnispredicted, all instructions
that were dispatched after the predicted branch instruction are flushed from the completion
queue and any results are flushed from the rename registers.
The BTIC is a cache of recently used branch target instructions. If the search for the branch
target hits in the cache, the first one or two branch instructions is available in the instruction
queue on the next cycle (shown in Figure 6-5). Two instructions are fetched on a BTIC hit,
unless the branch target is the last instruction in a cache block, in which case one instruction
is fetched.
In some situations, an instruction sequence creates dependencies that keep a branch
instruction from being resolved immediately, thereby delaying execution of the subsequent
Chapter 6. Instruction Timing
6-21
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