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Chapter 4
Exceptions
The OEA portion of the PowerPC architecture defines the mechanism by which PowerPC
processors implement exceptions (referred to as interrupts in the architecture specification).
Exception conditions may be defined at other levels of the architecture. For example, the
VISA defines conditions that may cause floating-point exceptions; the OEA defines the
mechanism by which the exception is taken.
The PowerPC exception mechanism allows the processor to change to supervisor state as a
result of unusual conditions arising in the execution of instructions and from external
signals, bus errors, or various internal conditions. When exceptions occur, information
about the state of the processor is saved to certain registers and the processor begins
execution at an address (exception vector) predetermined for each exception. Processing of
exceptions begins in supervisor mode.
Although multiple exception conditions can map to a single exception vector, often a more
specific condition may be determined by examining a register associated with the
exception-for example, the DSISR and the floating-point status and control register
(FPSCR). Also, software can explicitly enable or disable some exception conditions.
The PowerPC architecture requires that exceptions be taken in program order; therefore,
although a particular implementation may recognize exception conditions out of order, they
are handled strictly in order with respect to the instruction stream. When an instruction-
caused exception is recognized, any unexecuted instructions that appear earlier in the
instruction stream, including any that have not yet entered the execute state, are required to
complete before the exception is taken. For example, if a single instruction encounters
mUltiple exception conditions, those exceptions are taken and handled sequentially.
Likewise, exceptions that are asynchronous and precise are recognized when they occur,
but are not handled until all instructions currently in the execute stage successfully
complete execution and report their results.
To prevent loss of state information, exception handlers must save the information stored
in the machine status save/restore registers, SRRO and SRRI, soon after the exception is
taken to prevent this information from being lost due to another exception being taken.
Because exceptions can occur while an exception handler routine is executing, multiple
exceptions can become nested. It is up to the exception handler to save the necessary state
information if control is to return to the excepting program.
Chapter 4. Exceptions
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