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1.2.3 Memory Management Units (MMUs)
The MPC750's MMUs support up to 4 Petabytes (2
52 )
of virtual memory and 4 Gigabytes
(2
32 )
of physical memory for instructions and data. The MMUs also control access
privileges for these spaces on block and page granularities. Referenced and changed status
is maintained by the processor for each page to support demand-paged virtual memory
systems.
The LSU calculates effective addresses for data loads and stores; the instruction unit
calculates effective addresses for instruction fetching. The MMU translates the effective
address to determine the correct physical address for the memory access.
The MPC750 supports the following types of memory translation:
Real addressing mode-In this mode, translation is disabled by clearing bits in the
machine state register (MSR): MSR[IR] for instruction fetching or MSR[DR] for
data accesses. When address translation is disabled, the physical address is identical
to the effective address.
Page address translation-translates the page frame address for a 4-Kbyte page size
• Block address translation-translates the base address for blocks (128 Kbytes to 256
Mbytes)
If
translation is enabled, the appropriate MMU translates the higher-order bits of the
effective address into physical address bits. The lower-order address bits (that are
untranslated and therefore, considered both logical and physical) are directed to the on-chip
caches where they form the index into the eight-way set-associative tag array. After
translating the address, the MMU passes the higher-order physical address bits to the cache
and the cache lookup completes. For caching-inhibited accesses or accesses that miss in the
cache, the untranslated lower-order address bits are concatenated with the translated
higher-order address bits; the resulting 32-bit physical address is used by the memory unit
and the system interface, which accesses external memory.
The TLBs store page address translations for recent memory accesses. For each access, an
effective address is presented for page and block translation simultaneously. If a translation
is found in both the TLB and the BAT array, the block address translation in the BAT array
is used. Usually the translation is in a TLB and the physical address is readily available to
the on-chip cache. When a page address translation is not in a TLB, hardware searches for
one in the page table following the model defined by the PowerPC architecture.
Instruction and data TLBs provide address translation in parallel with the on-chip cache
access, incurring no additional time penalty in the event of a TLB hit. The MPC750's TLBs
are 128-entry, two-way set-associative caches that contain instruction and data address
translations. The MPC750 automatically generates a TLB search on a TLB miss.
1-12
MPC750 RISC Microprocessor User's Manual
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