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Four 32-bit counters in the MPC750 count occurrences of software-selectable events. Two
control registers (MMCRO and MMCR1) are used to control performance monitor
operation. The counters and the control registers are supervisor-level SPRs; however, in the
MPC750, the contents of these registers can be read by user-level software using separate
SPRs (UMMCRO and UMMCRl). Control fields in the MMCRO and MMCRI select the
events to be counted, can enable a counter overflow to initiate a performance monitor
exception, and specify the conditions under which counting is enabled.
As with other PowerPC exceptions, the performance monitor interrupt follows the normal
PowerPC exception model with a defined exception vector offset (OxOOFOO). Its priority is
below the external interrupt and above the decrementer interrupt.
11.1 Performance Monitor Interrupt
The performance monitor provides the ability to generate a performance monitor interrupt
triggered by a counter overflow condition in one of the performance monitor counter
registers (PMCI-PMC4), shown in Figure 11-3. A counter is considered to have
overflowed when its most-significant bit is set. A performance monitor interrupt may also
be caused by the flipping from 0 to 1 of certain bits in the time base register, which provides
a way to generate a time reference-based interrupt.
Although the interrupt signal condition may occur with MSR[EE]
=
0, the actual exception
cannQt be taken until MSR[EE]
=
1.
As a result of a performance monitor exception being signaled, the action taken depends on
the type of event that caused the condition, which are as follows:
• Threshold-related events-When a threshold event signals a performance monitor
exception, the addresses of the instruction that caused the counter to overflow is
saved in the SIA register.
•
Programmable events-To help track which part of the code was being executed
when an exception was signaled, the address of the last completed instruction during
that cycle is saved in the SIA.
Exception handling for the performance monitor interrupt exception is described in Section
4.5.13, "Performance Monitor Interrupt (OxOOFOO)."
11-2
MPC750 RISC Microprocessor User's Manual
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