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A
AACK (address acknowledge) signal, 7-14
ABB (address bus busy) signal, 7-5, 8-8
Address bus
address tenure, 8-7
address transfer
An, 7-7
APE,8-13
APn, 7-7
address transfer attribute
CI,7-12
GBL,7-13
TBST, 7-12, 8-14
TSIZn, 7-11, 8-13
TTn, 7-8, 8-13
WT,7-13
address transfer start (TS), 7-6, 8-12
address transfer termination
AACK,7-14
ARTRY, 7-14
terminating address transfer, 8-17
arbitration signals, 7-4, 8-8
bus parking, 8-11
Address translation,
see Memory management unit
Addressing modes, 2-35
Aligned data transfer, 8-15, 8-17
Alignment
data transfers, 8-15
exception, 4-18
misaligned accesses, 2-29
rules, 2-29
An (address bus) signals, 7-7
APE (address parity error) signal, 8-13
APn (address parity) signals, 7-7
Arbitration, system bus, 8-10, 8-19
Arithmetic instructions
floating-point, A-20
integer, A-17
ARTRY (address retry) signal, 7-14
B
BG (bus grant) signal, 7-4, 8-8
Block address translation
block address translation flow, 5-12
definition, 1-12
Index
INDEX
registers
description, 2-5
initialization, 5-21
selection of block address translation, 5-9
Boundedly undefined, definition 2-33
BR (bus request) signal, 7-4, 8-8'
Branch fall-through, 6-18
Branch folding, 6-18
Branch instructions
address calculation, 2-53
condition register logical, 2-54, A-26
description, A-25
list of instructions, 2-54, A-25
system linkage, 2-55, 2-65, A-26
trap, 2-55, A-26
Branch prediction, 6-1, 6-22
Branch processing unit
branch instruction timing, 6-23
execution timing, 6-18
latency, branch instructions, 6-31
overview, 1-9
Branch resolution
definition, 6-1
resource requirements, 6-30
BTIC (branch target instruction cache), 6-9
Burst data transfers
64-bit data bus, 8-15
transfers with data delays, timing, 8-32
Bus arbitration,
see Data bus
Bus configurations, 8-34
Bus interface unit (BID), 3-2, 3-30
Bus transactions and Ll cache, 3-22
Byte ordering, 2-35
c
Cache
bus interface unit, 3-2, 3-30
cache arbitration, 6-11
cache block, definition, 3-3
cache characteristics, 3-1
cache coherency
description, 3-5
overview, 3-25
reaction to bus operations, 3-26
cache control, 3-13
Index-1
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