Table of Contents
Advertisement
Figure 9-2 shows a burst read-write-read memory access sequence when the L2 cache
interface is configured with flow-through burst SRAM.
SRAMClk
L2CE
L2WE
SRAMAddress
I
SRAMMemory
SRAMData
I
Note:
R
xtr
indicates where an extra read cycle is signaled to keep the burst RAM driving the
data bus for the last read.
Figure 9-2. Burst Read-Write-Read L2 Cache Access (Flow-Through)
Figure 9-3 shows a burst read-modify-write memory access sequence when the L2 cache
interface is configured with flow-through burst SRAM.
SRAMClk
L2WE
SRAMAddress
SRAMMemory
SRAMData
I
Note:
R
xlr
indicates where an extra read cycle is signaled to keep the burst RAM driving the
data bus for the last read.
Figure 9-3. Burst Read-Modify-Write L2 Cache Access (Flow-Through)
9·10
MPC750 RISC Microprocessor User's Manual
Advertisement
Table of Contents
