Table of Contents
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INDEX
instruction cache block fill, 3-21
read operation, 3-23
response to snooped bus transactions, 3-26
single-beat write operations, 8-29
Optional instructions, A-41
Overview, 1-1
p
Page address translation
definition, 1-12
page address translation flow, 5-28
page size, 5-21
selection of page address translation, 5-9, 5-16
TLB organization, 5-26
Page history status
cases of dcbt and dcbtst misses, 5-22
Rand C bit recording, 5-12, 5-21-5-25
Page table updates, 5-34
Performance monitor
event counting, 11-11
event selecting, 11-12
perfonnance monitor interrupt, 4-20, 11-2
performance monitor SPRs, 11-3
purposes, 11-1
registers, 11-3
warnings, 11-12
Phase-locked loop, 10-3
Physical address generation, 5-1
Pipeline
instruction timing, definition, 6-2
pipeline stages, 6-7
pipelined execution unit, 6-4
superscalar/pipeline diagram, 6-5
PMCI and PMC2 registers, 1-26
PMCn (performance monitor counter)
registers, 2-16, 4-20, 11-6
Power and ground signals, 7-30
Power management
doze mode, 10-3
doze, nap, sleep, DPM bits, 2-13
dynamic power management, 10-1
full-power mode, 10-2
nap mode, 10-3
programmable power modes, 10-2
sleep mode, 10-4
software considerations, 10-5
PowerPC architecture
instruction list, A-I, A-9, A-17
operating environment architecture (OEA), xxviii,
1-21
user instruction set architecture (UISA), xxviii,
1-21
virtual environment architecture (VEA), xxviii,
1-21
Index-6
Priorities, exception, 4-4
Process switching, 4-12
Processor control instructions, 2-56, 2-60, 2-65, A-27
Program exception, 4-18
Program order, definition, 6-2
Programmable power states
doze mode, 10-3
full-power mode with DPM enabled/disabled, 10-2
nap mode, 10-3
sleep mode, 10-4
Protection of memory areas
no-execute protection, 5-14
options available, 5-11
protection violations, 5-16
PVR (processor version register), 2-5
Q
QACK (quiescent acknowledge) signal, 7-24
QREQ (quiescent request) signal, 7-24, 8-35
Qualified bus grant, 8-8
Qualified data bus grant, 8-20
R
Read operation, 3-26
Read-atomic operation, 3-26
Read-with-intent-to-modify operation, 3-26
Real address (RA), see Physical address generation
Real addressing mode (translation disabled)
data accesses, 5-12, 5-20
instruction accesses, 5-12, 5-20
support for real addressing mode, 5-2
Referenced (R) bit maintenance recording, 5-12,
5-22,5-31
Registers
implementation-specific
rCTC, 2-21,10-11
L2CR, 2-24, 9-4
MMCRO, 2-14, 4-20, 11-3
MMCRl, 2-16, 4-20,11-5
SIA, 2-20, 4-21
THRMn, 2-21, 10-7
UMMCRO, 2-15
UMMCRI,2-16
UPMCn, 2-20
USIA,2-20
MPC750 programming model, 2-2
perfonnance monitor registers, 2-14
reset settings, 2-27
SPR encodings, 2-58
supervisor-level
BAT registers, 2-5
DABR,2-7
DAR,2-6
MPC750 RISC Microprocessor User's Manual
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