Motorola MPC750 User Manual page 413

Table A-28. Segment Register Manipulation Instructions.
Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
mfsr
1,2
31 D 595
mfsrin 1,2
31 D 659
mtsr 1,2
31 S 210
mtsrd 1,2
31 S 82
mtsrdin 1,2
31 S 114
mtsrin 1,2
31 S 242
Notes:
1 Supervisor-level instruction
2 Optional 64-bit bridge instruction
Table A-29. Lookaside Buffer Management Instructions
Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
slbia 1 ,2,3
31 498
slbie 1 ,2,3
31 434
tibia 1,2,4
31 370
t1bie 1,2
31
306
t1bsync 1 ,2
31
566
Notes:
1 Supervisor-level instruction
2 Optional instruction
3 64-bit instruction
4
32-bit instruction not implemented by the MPC750
Table A-30. External
Control Instructions
Name 0 5 6 7 8 9 10 11 12131415161718192021 22232425262728293031
eCiWX~
___ 3_1 __
~
__________ 4-________
~
__________ 4-____________________
4-~
ecowx. 31
D A
B 310
I
S
A B
438
A-28 MPC750 RISC Microprocessor User's Manual