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Paragraph
Number
7.2.9.10
7.2.9.10.1
7.2.9.10.2
7.2.9.11
7.2.9.12
7.2.9.13
7.2.9.14
7.2.9.15
7.2.9.16
7.2.9.17
7.2.10
7.2.11
7.2.11.1
7.2.11.2
7.2.11.3
7.2.12
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.2
8.2.1
8.2.2
8.3
8.3.1
8.3.2
8.3.2.1
8.3.2.2
8.3.2.2.1
8.3.2.2.2
8.3.2.2.3
8.3.2.2.4
8.3.2.3
8.3.2.4
8.3.2.4.1
8.3.3
xii
CONTENTS
Title
Page
Number
L2 Data Parity (L2DP[0-7]) ....................................................................... 7-26
L2 Data Parity (L2DP[0-7])-Output ................................................... 7-26
L2 Data Parity (L2DP[0-7])-Input ...................................................... 7-26
L2 Chip Enable (L2CE)-Output .............................................................. 7-26
L2 Write Enable (L2WE)-Output ............................................................ 7-27
L2 Clock Out A (L2CLK_OUTA)-Output .............................................. 7-27
L2 Clock Out B (L2CLK_OUTB)-Output .............................................. 7-27
L2 Sync Out (L2SYNC_OUT)-Output ................................................... 7-27
L2 Sync In (L2SYNC_IN)-Input. ............................................................ 7-28
L2 Low-Power Mode Enable (L2ZZ)-Output ......................................... 7-28
IEEE 1149.1a-1993 Interface Description ..................................................... 7-28
Clock Signals .................................................................................................. 7-29
System Clock (SYSCLK)-Input .............................................................. 7-29
Clock Out (CLK_OUT)-Output .............................................................. 7-29
PLL Configuration (PLL_CFG[0-3])-Input.. .......................................... 7-30
Power and Ground Signals ............................................................................. 7-30
Chapter 8
MPC750 System Interface Overview ................................................................... 8-1
Operation of the Instruction and Data Ll Caches ............................................ 8-2
Operation of the L2 Cache ............................................................................... 8-4
Operation of the System Interface .................................................................... 8-4
Direct-Store Accesses ....................................................................................... 8-5
Memory Access Protocol. ..................................................................................... 8-6
Arbitration Signals ............................................................................................ 8-8
Address Pipelining and Split-Bus Transactions ............................................... 8-9
Address Bus Tenure ............................................................................................ 8-10
Address Bus Arbitration ................................................................................. 8-10
Address Transfer ............................................................................................ 8-12
Address Bus Parity ..................................................................................... 8-13
Address Transfer Attribute Signals ............................................................ 8-13
Transfer Type (TT[0-4]) Signals ........................................................... 8-13
Transfer Size (TSIZ[0-2]) Signals ......................................................... 8-13
Write-Through (WT) Signal ................................................................... 8-14
Cache Inhibit (CI) Signal ....................................................................... 8-14
Burst Ordering During Data Transfers ....................................................... 8-15
Effect of Alignment in Data Transfers ....................................................... 8-15
Alignment of External Control Instructions ........................................... 8-17
Address Transfer Termination ........................................................................ 8-17
MPC750 RISC Microprocessor User's Manual
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