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The bits in THRM3 are described in Table 2-17.
Table 2-17. THRM3 Bit Settings
Bits
Name
Description
0-17
-
Reserved for future use. System software should clear these bits when writing to the THRM3.
18-30
SITV
Sample interval timer value. Number of elapsed processor clock cycles before a junction
temperature vs. threshold comparison result is sampled for TIN bit setting and interrupt
generation. This is necessary due to the thermal sensor, DAC, and the analog comparator
settling time being greater than the processor cycle time. The value should be configured to allow
a sampling interval of 20 microseconds.
31
E
Enables the thermal sensor compare operation if either THRM1 [V] or THRM2[V] is set.
The THRM registers can be accessed with the mtspr and mfspr instructions using the
following SPR numbers:
THRM1 is SPR 1020
THRM2 is SPR 1021
THRM3 is SPR 1022
2.1.5 L2 Cache Control Register (L2CR)
The L2 cache control register, shown in Figure 2-12, is a supervisor-level,
implementation-specific SPR used to configure and operate the L2 cache. It is cleared by a
hard reset or power-on reset.
L2WT
L2DF
Reserved
o
1
2
3
4
6
7
8
9 10 11 12 13 14 15 16 17 18 19
30 31
Figure 2-12. L2 Cache Control Register (L2CR)
The L2 cache interface is described in Chapter 9, "L2 Cache Interface Operation." The
L2CR bits are described in Table 2-18.
2-24
MPC750 RISC Microprocessor User's Manual
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