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Sleep mode sequence
-
Set sleep bit (HIDO[lO]
= 1),
clear doze and nap bits (HIDO[8] and HIDO[9])
-
MPC750 asserts quiesce request (QREQ)
-
System asserts quiesce acknowledge (QACK)
-
MPC750 enters sleep mode after several processor clocks
•
Several methods of returning to full-power mode
-
Assert INT, SMI, or MCP interrupts
-
Assert hard reset or soft reset
•
PLL and DLL may be disabled and SYSCLK may be removed while in sleep mode
•
Return to full-power mode after PLL and SYSCLK are disabled in sleep mode
-
Enable SYSCLK
-
Reconfigure PLL into desired processor clock mode
-
System logic waits for PLL startup and relock time (100 llsec)
-
System logic asserts one of the sleep recovery signals (for example, INT or SMI)
-
Reconfigure DLL, wait for DLL relock (640 L2 clock cycles) and re-enable L2
cache through the L2CR
10.2.2 Power Management Software Considerations
Since the MPC750 is a dual-issue processor with out-of-order execution capability, care
must be taken in how the power management mode is entered. Furthermore, nap and sleep
modes require all outstanding bus operations to be completed before these power
management modes are entered. Normally, during system configuration time, one of the
power management modes would be selected by setting the appropriate HIDO mode bit.
Later on, the power management mode is invoked by setting the MSR[POW] bit. To ensure
a clean transition into and out of a power management mode, set the MSR[EE] bit to land
execute the following code sequence:
sync
mtmsr[POW
=
1]
isync
loop:
bloop
Chapter
10.
Power and Thermal Management
10-5
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