Sequential Control Field Definition - Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual

SQC — Sequential Control
The SQC field allows memory breakpoint B and trace occurrences to be suspended
until a qualifying event occurs. This field is cleared on test logic reset.
Table C-21 Sequential Control Field Definition
SQC[1:0]
Disable sequential control operation. Memory breakpoints and trace operation are unaf-
00
fected by this field.
Suspend normal trace counter operation until a breakpoint condition occurs for memory
breakpoint B. When this mode is selected, memory breakpoint B occurrences no longer
cause a breakpoint request to be generated. Instead, trace counter comparisons are sus-
01 pended until the first memory breakpoint B occurrence. After the first memory breakpoint
B occurrence, trace counter control is released to perform normally (assuming TME is
set). This allows a sequence of breakpoint conditions to be specified prior to trace count-
ing.
Qualify memory breakpoint B matches with a breakpoint occurrence for memory break-
point A. When this bit is set, memory breakpoint A occurrences no longer cause a break-
point request to be generated. Instead, memory breakpoint B comparisons are
10
suspended until the first memory breakpoint A occurrence. After the first memory break-
point A occurrence, memory breakpoint B is enabled to perform normally. This allows a
sequence of breakpoint conditions to be specified.
Combine the qualifications specified by the 01 and 10 encodings of this field. In this
mode, no breakpoint requests are generated, and trace count operation is enabled (when
11
TME is set) once a memory breakpoint B occurrence follows a memory breakpoint A
occurrence.
DR — CPU Debug Request Control
This control bit is used to request the CPU to enter debug mode unconditionally. The
CPU indicates that debug mode has been entered via the PM bits in the OnCE status
register. Once the CPU enters debug mode, it returns there even with a write to the
OCMR with GO and EX set until the DR bit is cleared. This bit is cleared on test logic
reset.
IDRE — Internal Debug Request Enable
This control bit is used to enable internally generated debug requests. The internal
debug request input to the OnCE control logic (IDR) may not be used in all implemen-
tations. In some implementations, the IDR control input may be connected and used
as an additional hardware debug request. This bit is cleared on test logic reset.
0 = Disable IDR input operation
1 = Enable IDR input operation
TME — Trace Mode Enable
The TME control bit enables the OnCE trace mode operation. This bit is cleared on
test logic reset. Trace operation is also affected by the SQC field described above.
0 = Disable trace operation
1 = Enable trace operation
FRZC — Freeze Control
This control bit is used in conjunction with memory breakpoint B registers to select
between asserting a breakpoint condition when a memory breakpoint B occurs, or
freezing the PC FIFO from further updates when memory breakpoint B occurs while
allowing the CPU to continue execution. The PC FIFO remains frozen until the FRZO
bit in the OSR is cleared.
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MMC2001
REFERENCE MANUAL