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Power Optimization
Another way to save power is to reduce memory traffic. Instead of using a color depth of 16-bits
per pixel, systems could use 8-bits per pixel to reduce the memory bandwidth for LCD refresh.
The output drivers for the PXA27x processor LCD data pins have programmable strength settings.
This feature allows for simple, software-based control of the output-driver impedance for the data
pins on the LCD bus. Use these registers to match the driver strength of the PXA27x processor to
LCD bus. The buffer strength should be set to the lowest possible setting (minimum drive strength)
that still allows for reliable bus performance. This minimizes the power usage of the LCD data
pins, which can be a major component of total system power, since in a typical system, these pins
are always driven while the screen is on. Refer to the
(LCDBSCNTR)"
information.
6.3.6
Voltage and Regulators
The PXA27x processor supports 1.8 V memory. Depending on the memory usage of applications,
there may be significant power savings using 1.8 V SDRAM compared to 2.5 V or 3.3 V SDRAM.
If no other devices in the system use 1.8 V, then users must consider the power savings compared
to the extra components and board real-estate to support 1.8 V.
6.3.7
Operating Mode Recommendations for Power Savings
6.3.7.1
Normal Mode
It may be require less power to run at a higher Intel XScale® core frequency/voltage to complete a
task and then drop the operating frequency and Intel XScale® core voltage than to run at a constant
frequency and voltage. Profile the OS and applications to determine the optimum Intel XScale®
core operating frequency. Use the lowest possible Intel XScale® core voltage to run at the required
frequency.
For lowest power consumption in normal mode:
•
Use Intel® Integrated Performance Primitives
•
Use Wireless Intel Speedstep® Technology
•
Use Intel® Power Manager
•
Use low-power modes when possible
•
Enable both caches
•
Use a caching policy of read allocate/write back when possible
•
Set the APD bit (see
•
Configure the System Memory Buffer Strength Control registers for the minimal setting for
reliable memory bus performance.
•
Configure the LCD Buffer Strength Control register for the minimal setting for reliable LCD
bus performance.
6.3.7.2
Idle Mode
Use idle mode only for brief periods of time when the Intel XScale® core is soon required to
perform calculations.
6-6
table in the Intel® PXA27x Processor Family Developer's Manual for more
Section
6.3.2)
Intel® PXA27x Processor Family Optimization Guide
"LCD Buffer Strength Control Register
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