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INTERRUPT CONTROL UNIT
Interrupts eliminate the need for polling by signalling the CPU that a peripheral device requires
servicing. The CPU then stops executing the main task, saves its state and transfers execution to
the peripheral-servicing code (the interrupt handler). At the end of the interrupt handler, the
CPU's original state is restored and execution continues at the point of interruption in the main
task.
8.2
MASTER MODE
Figure 8-1 shows a block diagram of the Interrupt Control Unit in Master mode. In this mode, the
ICU processes all interrupt requests, both external and internal. The three timer interrupt requests
share a single input, while the others are supported directly.
DMA
DMA
Timer 0 Timer 1 Timer 2
0
1
INT0 INT1 INT2 INT3
Interrupt
Priority
Resolver
Vector
To CPU Interrupt Request
Generation
Logic
F - Bus
A1506-A0
Figure 8-1. Interrupt Control Unit in Master Mode
8.2.1
Generic Functions in Master Mode
Several functions of the Interrupt Control Unit are common among most interrupt controllers.
This section describes how those generic functions are implemented in the Interrupt Control Unit.
8-2
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