Single Ended Host Bus Clocking Routing; Single Ended Clocking Topology - Cpu; Single Ended Clocking Topology; Lv Intel Pentium - Intel Pentium III Processor 512K Design Manual

4.2

Single Ended Host Bus Clocking Routing

LV Intel Pentium

using this clocking method, the BCLK signal (ball AC1) is used as the single-ended clock input to
the LV Intel Pentium
reference voltage and must be connected to the appropriate filter circuit described in "CLKREF
Filter Implementation" on page 27.
Figure 12 shows the topology that should be used for the LV Intel Pentium
traces. Please note that L0, L1, and L2 refer to trace lengths between the illustrated components.
Table 15 contains the recommended lengths and component values for this topology.
Figure 12. Single Ended Clocking Topology - CPU
Clock Driver
Figure 13 shows the topology that should be used for the chipset clock traces. Note that Ln refers to
trace lengths between the illustrated components. Table 15 contains the recommended lengths and
component values for this topology.
Figure 13. Single Ended Clocking Topology
Clock Driver
Design Guide
®
LV Intel Pentium
processor 512K platforms support single-ended host bus clock drivers. When
III
processor 512K. The BCLK#/CLKREF signal (ball AD1) is used as a
III
L0
Zo = 55 Ω Rs
L0
L0
L0
L0
®
III Processor 512K Dual Processor Platform
L1
Zo = 55 Ω
Lclkref
CLKREF
Filter
L1
R
S
L1
R
S
L2
R
S
L3
R
S
processor 512K clock
III
Processor
BCLK
+
CLKREF
–
Processor 1
Processor 2
Chipset
PLL
25