Serial Communications Unit Transfers - Intel 80C188EC User Manual

10.1.5.3

Serial Communications Unit Transfers

The Serial Communications Unit has two channels, each with its own receiver and transmitter.
Each of the DMA channels is assigned a Serial Communications Unit channel as follows:
•
DMA channel 0 supports the serial port 0 transmitter (TX0).
•
DMA channel 1 supports the serial port 0 receiver (RX0).
•
DMA channel 2 supports the serial port 1 transmitter (TX1).
•
DMA channel 3 supports the serial port 1 receiver (RX1).
The DMA request and interrupt request signals from the serial channels are identical. For exam-
ple, when serial channel 1 completes a reception, it pulses both the interrupt request signal and
the DMA request signal high for one clock cycle.
Servicing the serial ports with DMA transfers (instead of interrupt requests) provides a tremen-
dous gain in system throughput when blocks of serial data are transmitted and received. When
using DMA-driven serial port transfers, it is important to note that as the baud rate of the transfer
is increased, so does bus utilization by the DMA Unit. Using high baud rates or multiple channels
can degrade CPU performance. (See "DMA-Driven Serial Transfers" on page 10-34.)
10.1.5.4 Unsynchronized Transfers
DMA transfers can be initiated directly by the system software by selecting unsynchronized
transfers. Unsynchronized transfers continue, back-to-back, at the full bus bandwidth, until the
channel's transfer count reaches zero or DMA transfers are suspended by an NMI.
10.1.6 DMA Transfer Counts
Each DMA Unit maintains a programmable 16-bit transfer count value that controls the total
number of transfers the channel runs. The transfer count is decremented by one after each transfer
(regardless of data size). The DMA channel can be programmed to terminate transfers when the
transfer count reaches zero (also referred to as terminal count).
10.1.7 Termination and Suspension of DMA Transfers
When DMA transfers for a channel are terminated, no further DMA requests for that channel will
be granted until the channel is re-started by direct programming. A suspended DMA transfer tem-
porarily disables transfers in order to perform a specific task. A suspended DMA channel does
not need to be re-started by direct programming.
DIRECT MEMORY ACCESS UNIT
10-7