Channels 4 - 11 Blocks; Output Control; Layout Notes - Intel PXA27 Series Design Manual

22.3.3

Channels 4 - 11 Blocks

Channels 4 through 11 are eight additional independent channels each with its own counter, match
register, and control register. Each independent counter is clocked with any of these software
selectable clocks:
•
32.768 KHz clock for low power
•
13.0 MHz clock for high accuracy
•
Externally supplied clock for network sychronization
22.3.4

Output Control

This block collects the match signals from each timer channel and generates the following signals:
•
Match signals to the interrupt controller
•
Channel-output signals to the GPIO block
•
Watchdog-reset signal
22.4

Layout Notes

The EXT_SYNCx signals are clocked using a two-stage sychnronizer. Therefore, depending on the
setting of the OMCRx[CRES] bitfield, the signal must remained asserted for three clock periods of
the source clock.
Refer to Intel
PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for all AC timing
information.
®
Intel PXA27x Processor Family Design Guide
®
PXA270 Processor Electrical, Mechanical, and Thermal Specifications and Intel
§§
OS Timer Interface
®
II:22-3