Control Registers - Hitachi H8/300H Series Programming Manual

General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 1-9 shows the
stack.
Free area
SP (ER7)
Stack area
Figure 1-9 Stack

1.4.3 Control Registers

The control registers are the 24-bit program counter (PC) and the 8-bit condition-code register
(CCR).
(1) Program Counter (PC): This 24-bit counter indicates the address of the next instruction the
CPU will execute. The length of all CPU instructions is 16 bits (one word) or a multiple of 16 bits,
so the least significant PC bit is ignored. When an instruction is fetched, the least significant PC
bit is regarded as 0.
(2) Condition Code Register (CCR): This 8-bit register contains internal CPU status
information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z),
overflow (V), and carry (C) flags.
Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted
regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exception-
handling sequence.
Bit 6—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC,
and XORC instructions. This bit can also be used as an interrupt mask bit. For details see the
relevant microcontroller hardware manual.
10