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WATCHDOG TIMER/TIME-BASE TIMER/WATCH TIMER (SUB-CLOCK)
9.3.3 Watch timer control register (WTC)
The watch timer control register (WTC) selects clock signals, controls interrupts and intervals, and clears the
counter.
n Watch timer control register (WTC)
Clock timer control register
Address: 0000AA
Read/write →
Initial value →
[bit 7] WDCS
WDCS selects the clock source of the watchdog timer. When WDCS is 0, the clock output of the watch
timer is selected as the clock source of the watchdog timer; when WDCS is 1, the clock output of the
time-base timer is selected as the clock source of the watchdog timer.
Resets initialize WDCS to 1.
Note:
When WDCS is changed, there is a possibility that the watchdog count may become 1 count shorter
because the time-base timer and watch timer operate asynchronously. So, when changing WDCS,
clear the watchdog timer temporarily just before changing the clock mode.
[bit 6] SCE
SCE indicates that the oscillation stabilization wait time for the sub-clock is elapsed. When this bit is 0, it
indicates that the oscillation stabilization wait time is in progress. The oscillation stabilization wait time is
14
fixed to 2
cycles (sub-clock). SCE is initialized to 0 at power-on reset or at stop.
[bit 5] WTIE
WTIE enables interval interrupts by the watch timer. When WTIE is 1, interrupts are enabled; when it is
0, interrupts are disabled. Resets initialize WTIE to 0. The WTIE bit can be both read and written.
[bit 4] WTOF
WTOF is the interrupt request flag for the watch timer. When WTOF is set to 1 when the WTIE bit is 1, an
interrupt request is issued. WTOF is set to 1 at the interval set by the WTC2 to WTC0 bits. WTOF is
cleared by writing 0 to WTOF, transitions to the stop mode, or by a reset. Writing 1 to WTOF has no
meaning.
When WTOF is read by a read-modify-write instruction, 1 is read.
[bit 3] WTR
WTR clears all bits of the watch timer counter to 0. Writing 0 to WTR clears the clock counter. Writing 1
to WTR has no meaning. At reading, 1 is always read from WTR.
7
6
SCE
WDCS
H
(R/W)
(R)
(1)
(0)
Fig. 9.4 Watch Timer Control Register
5
4
3
WTIE
WTR
WTOF
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
9-9
2
1
0
WTC2
WTC1
WTC0
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
← Bit No.
WTC
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