Instruction Pipeline With Off-Chip Memory Accesses; Table 7-2 Instruction Pipelining - Motorola DSP56800 Manual

Operation
Fetch
Decode
Execute
Table 7-2 demonstrates pipelining. "F1," "D1," and "E1" refer to the fetch, decode, and execute operations
of the first instruction, respectively. The third instruction, which contains an instruction extension word,
takes two instruction cycles to execute. Although it takes three instruction cycles (six machine cycles) for
the pipeline to fill and the first instruction to execute, an instruction usually executes on each instruction
cycle thereafter (two machine cycles).
7.2.2

Instruction Pipeline with Off-Chip Memory Accesses

The three sets of internal on-chip address and data buses (XAB1/CGDB, XAB2/XDB2, PAB/PDB) allow
for fast memory access when memories are being accessed on-chip. The DSP can perform memory
accesses on all three bus pairs in a single instruction cycle, permitting the fetch of an instruction
concurrently with up to two accesses to the X data memory. Thus, for applications where all program and
data is located in on-chip memory, there is no speed penalty when performing up to three memory accesses
in a single instruction.
Similarly, the external address and data bus also allows for fast program execution. For the case where
only program memory is external to the chip or only X data memory is external (XAB1/CDGB bus pair),
the DSP chip will still execute programs at full speed if there are no wait states programmed on the
external bus by the user. For the case where an instruction requires an external program fetch and an
external X data memory access simultaneously, the instruction will still operate correctly. The instruction
is automatically stretched an additional instruction cycle so that the two external accesses may be
performed correctly, and wait states are inserted accordingly. All this occurs transparently to the user to
allow for easier program development.
This information is summarized in Table 7-3, which shows how the chip automatically inserts instruction
cycles and wait states for an instruction that is simultaneously accessing program and data memory. For
dual parallel read instructions, the second X memory access that uses XAB2/XDB2 must always be done
to on-chip memory. This second access may never access external off-chip memory.
Table 7-2. Instruction Pipelining
Instruction Cycle
1 2 3 4
F1 F2 F3 F3e
D1 D2 D3
E1 E2
Interrupts and the Processing States
Normal Processing State
5 6 7 •
F4 F5 F6 •
D3e D4 D5 •
E3 E3e E4 •
• •
• •
• •
• •
7-3