Fujitsu F2MC-16LX Hardware Manual page 292

CHAPTER 17 UART
■ Initialization
The settings of the control registers used in the CLK-synchronous mode are shown below.
Table 17.4-5 Settings of Control Registers Used in CLK-synchronous Mode
Register
name
SMR register
SCR register
SSR register
■ Start of Communication
Communication is started by writing data into the SODR register. Even in the case of a receive-
only operation, it is always necessary to write temporary transmitter data into the SODR
register.
■ End of Communication
The end of communication can be confirmed by the fact that the RDRF flag of the SSR register
is changed to "1".
Check the ORE bit of the SSR register to see if communication has been completed normally.
276
Bit name
MD1, MD0 10
B
CS2, CS1,
Specifies clock input.
CS0
"1" for communication prescaler or internal timer and "0" for
SCKE
external clock.
SOE "1" for transmit operation and 0 for receive-only operation.
PEN "0"
P, SBL, A/D These bits are not significant.
CL "1" (8-bit data)
REC "0" (for initialization)
RXE, TXE Set at least either of the bits to "1".
RIE "1" if using an interrupt; otherwise, "0".
TIE "0"
Setting