Fujitsu F2MC-16LX Hardware Manual page 142

CHAPTER 6 MEMORY ACCESS MODES
Table 6.2-7 Function of HDE (Input/Output Enable Bit Of Hold Related Pins)
HDE
0
1
[bit12] IOBS
The IOBS bit specifies a bus size for external access to the area 0000C0
external 16-bit data bus mode. This bit controls the size as listed in Table 6.2-8.
Table 6.2-8 Function of IOBS (Bus Size Specification Bit)
IOBS
0
1
[bit11] HMBS
he HMBS bit specifies a bus size for external access to the area 800000
external 16-bit data bus mode. This bit controls the size as listed in Table 6.2-9.
Table 6.2-9 Function of HMBS (Bus Size Specification Bit)
HMBS
0
1
[bit10] WRE
The WRE bit controls output of the external write signal (in external data bus 16-bit mode,
the WRH and WRL pins; and in external data bus 8-bit mode, the WRL pin) as listed in
Table 6.2-10.
In an external 8-bit data bus mode, P33 operates as an I/O port pin regardless of the set
value of this bit.
Table 6.2-10 Function of WRE (External Write Signal Output Control Bit)
WRE
0
1
126
I/O port (P35 and P34) operation (Prohibits hold function input/output.)[Initial
value]
Enables input of hold request (HRQ)/output of hold acknowledge (HAK).
16-bit bus access [Initial value]
8-bit bus access
16-bit bus access [Initial value for external vector mode 1]
8-bit bus access [Initial value for external vector mode 0]
I/O port (P33, P32) operation (Prohibits write signal output.) [Initial value]
Enables output of the write strobe signal (WRH and WRL or only WRL)
Function
Function
Function
Function
to 0000FF in an
H H
to FFFFFF in an
H H