Fujitsu F2MC-16LX Hardware Manual page 226

CHAPTER 12 8/16-BIT PPG
■ Relationship between the Reloaded Value and Pulse Width
As shown in Table 12.4-1, the pulse width of the output pulse signal is obtained by multiplying
the value written in the reload register plus "1" by the count cock cycle. Note that when the
reload register value is 00
0000 during 16-bit PPG operation, the pulse width equals one count clock cycle. When the
H
reload register value is FF
cycles. Similarly, when the reload register value is FFFF
pulse width equals 65536 count clock cycles. The following expressions are for calculating a
pulse width:
Pl = T × (L + 1)
Ph = T × (H + 1)
L:
H:
T:
Ph: High-level pulse width
Pl:
210
during 8-bit PPG operation and when the reload register value is
H
during 8-bit PPG operation, the pulse width equals 256 count clock
H
PRLL value
PRLH value
Input clock cycle
Low-level pulse width
during 16-bit PPG operation, the
H