Fujitsu F2MC-16LX Hardware Manual page 478

INDEX
Input Capture Data Register
Input Capture Data Register (IPCO0 to IPCO3)
.......................................................... 172
Input Resistor Register
Input Resistor Registers (RDR0 and RDR1)........ 144
Input/Output Timing
Start/Stop Timing of Shift Operation and Input/Output
Timing ............................................... 297
Instruction
Description of Instruction Presentation Items and
Symbols ............................................ 414
2
F MC-16LX Instruction List ............................. 417
Instruction Types.............................................. 393
Interrupt Stop Instruction .................................... 59
Occurrence of Exceptions because of Executing
Undefined Instructions........................... 80
Structure of Instruction Map.............................. 431
Using the "DIV A,Ri" and "DIVW A,RWi"
Instructions ........................................... 47
Instruction Map
Structure of Instruction Map.............................. 431
INT
Competition Among the SCC,MSS,and INT Bits
.......................................................... 311
Intermittent CPU Operation
Intermittent CPU Operation Function ................. 108
Internal Clock
Internal Clock Operations ................................. 188
Internal Clock Mode
Input Pin Function (for the Internal Clock Mode)
.......................................................... 190
Internal Resource
Hardware Interrupt Request during Writing
to the Internal Resource Area ................. 59
Internal Shift Clock Mode
Internal Shift Clock Mode ................................. 293
Internal timer
Internal timer ................................................... 272
Interrupt
8/16-bit PPG Interrupt ...................................... 206
Example of Procedure for Using Hardware Interrupts
............................................................ 65
Extended Intelligent I/O Service (EI
and Interrupts...................................... 189
Five Flags (PE,ORE,FRE,RDRF,and TDRE) and
Two Interrupt Sources ......................... 277
Hardware Interrupt Request during Writing
to the Internal Resource Area ................. 59
Interrupt Causes ................................................. 53
Interrupt Flag Setting Timing in Operating Modes
.......................................................... 277
Interrupt Function of the I/O Extended Serial Interface
.......................................................... 300
Interrupt Vectors ................................................ 56
Multiple Interrupts.............................................. 59
462
Interrupt Causes
Interrupt Control Register
Interrupt Generating Module
Interrupt Level Mask Register
Interrupt Stop Instruction
Interrupt Suppression
Interrupt Suppression Instructions
Interrupt Vectors
Interrupt/DTP Enable Register
Interrupt/DTP Source Register
Interval Interrupt
IOA
IPCO
2
OS) Function
ISCS
ISD
ISEL
Notes on Software Interrupts............................... 67
Notes on the Use of Hardware Interrupts .............. 60
Operating Flow for Hardware Interrupts............... 64
Operation of Software Interrupts ......................... 66
Operations of Hardware Interrupts....................... 61
Overview of Hardware Interrupts ........................ 58
Overview of Interrupts ....................................... 52
Overview of Software Interrupts.......................... 66
Processing Time for a Hardware Interrupt ............ 63
Saving a Register to the Stack at an Interrupt
........................................................... 59
Structure of Hardware Interrupts ......................... 58
Structure of Software Interrupts........................... 66
Interrupt Causes................................................. 53
Interrupt Control Register (ICR).......................... 70
Operation of the Delayed Interrupt Generating Module
......................................................... 229
Interrupt Level Mask Register (ILM) ................... 37
Interrupt Stop Instruction .................................... 59
Restrictions on Interrupt Suppression and
Prefix Instructions................................. 46
Interrupt Suppression Instructions ....................... 46
Interrupt Vectors................................................ 56
Interrupt/DTP Enable Register (ENIR)............... 218
Interrupt/DTP Source Register (EIRR)............... 218
Interval Interrupt Function ................................ 151
I/O Register Address Pointer (IOA) ..................... 74
Input Capture Data Register (IPCO0 to IPCO3)
......................................................... 172
2
OS Status Register (ISCS).............................. 74
EI
Expanded Intelligent I/O Service Descriptor (ISD)
........................................................... 73
Port Selection Register (ISEL) .......................... 316