Fujitsu F2MC-16LX Hardware Manual page 215

[bit4] PIE0 (Ppg Interrupt Enable)
The PIE0 bit enables or disables PPG interrupts as shown in Table 12.3-3.
If this bit is "1", an interrupt request is issued when PUF0 is set to "1".
If this bit is "0", no interrupt request is issued.
Table 12.3-3 PIE0 (PPG Interrupt Enable Bit) Function
PIE0
0 Interrupt disabled [initial value]
1 Interrupt enabled
[bit3] PUF0 (Ppg Underflow Flag)
The PUF0 bit is a PPG counter underflow bit. Table 12.3-4 shows the relationship between
this bit and the 8-bit down counter PCNT.
Table 12.3-4 PUF0 (PPG Counter Underflow Bit) Function
PUF0
0 Underflow not detected in down counter PCNT [initial value]
1 Underflow detected in down counter PCNT
In the 8-bit PPG 2-ch mode and the 8-bit prescaler + 8-bit PPG mode, an underflow caused
when the ch.0 counter value changes from 00
mode, an underflow caused when the ch.1/ch.0 counter value changes from 0000
sets the bit to "1". This bit is set to 0 by writing "0" to this bit.
Writing "1" to this bit has no meaning.
At read in read-modify-write operation, "1" is read from this bit.
[bit0] Reserved bit
Bit0 is a reserved bit. Whenever setting PPGC0, be sure to set this bit to "1".
12.3 Registers in the 8/16-Bit PPG
Function
Function
to FF sets the bit to "1". In the 16-bit PPG 1-ch
H H
to FFFF
H H
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