CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT
Note:
Normally, the CPU executes interrupt processing after executing the instruction following the
instruction causing the watch mode. If a transition to the watch mode and acceptance of an external
bus hold request occur simultaneously, the CPU may execute interrupt processing before executing
the next instruction.
After the watch mode is released, the standby control circuit waits for PLL clock oscillation to become
stable. When the PLL clock is not used, set the MCS bit to "1" using the instruction immediately after
the reset or interrupt destination.
To release the external interrupt clock mode, set the external interrupt request level to "H". The "L"-
level interrupt setting may cause malfunctions. The clock mode cannot be released by an edge
interrupt request.
102