Fujitsu F2MC-16LX Hardware Manual page 139

Mb90550a/b series, 16-bit
Hide thumbs Also See for F2MC-16LX:
Table of Contents

Advertisement

[bit9 , bit8] LMR1 and LMR0
The LMR1 and LMR0 bits specify an automatic wait function for external access to area
002000
to 7FFFFF
H
H
Table 6.2-3 Function of LMR1 and LMR0 (Automatic Wait Function Specification Bits)
LMR1
LMR0
0
0
0
1
1
0
1
1
6.2 External Memory Access (External Bus Pin Control Circuit)
. The two bits are combined as listed in Table 6.2-3.
Prohibits automatic wait. [Initial value]
Inserts automatic 1-machine cycle wait at external access.
Inserts automatic 2-machine cycle wait at external access.
Inserts automatic 3-machine cycle wait at external access.
Function
123

Advertisement

Table of Contents
loading

Table of Contents