Clock Control Register (Iccr) - Fujitsu F2MC-16LX Hardware Manual

2
CHAPTER 19 I C INTERFACE

19.3.3 Clock Control Register (ICCR)

The clock control register (ICCR) controls the operation of the I
the frequency of the serial clock.
■ Clock Control Register (ICCR)
Clock control register
Address: ch .0 00002E
ch.1 000034
Read/write
Initial value
[bit5] EN (Enable)
The EN bit enables the I
register and the BCR register (except for the BER and BEIE bits) are cleared. When the
BER bit is set, this bit is cleared.
Table 19.3-17 Functions of the EN (Enable) Bit
EN
0
1
[bit4 to bit0] CS4 to CS0 (Clock period select 4 to 0)
These bits are used to set the frequency of the serial clock.
fsck, the frequency of the shift clock, is set according to the following calculation:
312
Figure 19.3-4 Clock Control Register (ICCR)
7 6
bit
H
EN
H
(-) (-) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(-) (-) ( 0)
2
C interface to operate. When this bit is "0", the bits of the BSR
Operation disabled [Initial value]
Operation enabled
fsck =
φ
: Machine clock
5 4 2
3
CS4 CS3 CS2
(X) (X) (X) (X)
Operation status
φ
m × n + 4
2
C interface and sets
1 0
ICCR
CS1
CS0
(X)