Fujitsu F2MC-16LX Hardware Manual page 480

Mb90550a/b series, 16-bit
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INDEX
ODR
Output Pin Register (ODR4).............................. 143
ORE
Five Flags (PE,ORE,FRE,RDRF,and TDRE) and
Two Interrupt Sources......................... 277
Oscillating Clock Frequency
Oscillating Clock Frequency and Serial Clock Input
Frequency........................................... 374
Oscillation Stabilization Time
Setting the Oscillation Stabilization Time ........... 109
OTPROM
OTPROM Programming Yield .......................... 454
Procedure for Programming the OTPROM ......... 453
Screening Conditions Recommended
for the OTPROM ................................ 454
Output Compare
16-bit Output Compare Operations..................... 176
16-bit Output Compare Timing.......................... 177
Output Compare (x 4) ....................................... 160
Output Pin Register
Output Pin Register (ODR4).............................. 143
P
Package
External Dimensions of the FPT-100P-M05 Package
.............................................................. 8
External Dimensions of the FPT-100P-M06 Package
.............................................................. 7
PACSR
Program Address Detection Control Register
(PACSR) ............................................ 329
PADR
Program Address Detection Registers
(PADR0 and PADR1).......................... 329
Pause Mode
2
Example of EI
OS Activation in Pause Mode
.......................................................... 248
Pause Mode ..................................................... 243
PC
Program Counter (PC) ........................................ 39
PCB
Program Bank Register (PCB) ............................. 41
PDRx
Port Data Register (PDRx) ................................ 140
PE
Five Flags (PE,ORE,FRE,RDRF,and TDRE) and
Two Interrupt Sources ......................... 277
Peripheral Devices
Conditions of Peripheral Devices Connected
Externally when DTP is Used ............... 224
Pin Arrangement
Pin Arrangement of the FTP-100P-M05 ............... 10
Pin Arrangement of the FTP-100P-M06 ................. 9
464
Pin Functions
Description of the Pin Functions.......................... 11
Port Data Direction Register
Port Data Direction Register (DDRx)................. 142
Port Data Register
Port Data Register (PDRx)................................ 140
Port Selection Register
Port Selection Register (ISEL) .......................... 316
PPG
8/16-bit PPG Interrupt ...................................... 206
8/16-bit PPG Operation .................................... 206
8/16-bit PPG Operation Modes.......................... 208
Block Diagrams of the 8-bit PPG....................... 195
Overview of the 8/16-bit PPG ........................... 194
PPG Output Operation...................................... 209
Registers in the 8/16-bit PPG ............................ 197
PPG0 Operation Mode Control Register
PPG0 Operation Mode Control Register (PPGC0)
......................................................... 198
PPG0/1 Output Pin Control Register
PPG0/1 Output Pin Control Register (PPGE)
......................................................... 203
PPG1 Operation Mode Control Register
PPG1 Operation Mode Control Register (PPGC1)
......................................................... 200
PPGC
PPG0 Operation Mode Control Register (PPGC0)
......................................................... 198
PPG1 Operation Mode Control Register (PPGC1)
......................................................... 200
PPGE
PPG0/1 Output Pin Control Register (PPGE)
......................................................... 203
Prefix
Common Register Bank Prefix (CMR)................. 45
Flag Change Suppression Prefix (NCC) ............... 45
Prefix Codes
In the Case of Consecutive Prefix Codes .............. 46
Prefix Instructions
Restrictions on Interrupt Suppression and
Prefix Instructions................................. 46
Prescaler
Communication Prescaler ................................. 271
PRLL
Reload Registers (PRLL/PRLH)........................ 205
Processor Status
Processor Status (PS) ......................................... 36
Program Address Detection Control Register
Program Address Detection Control Register
(PACSR)............................................ 329
Program Address Detection Register
Program Address Detection Registers (PADR0 and
PADR1) ............................................. 329

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