Fujitsu F2MC-16LX Hardware Manual page 90

CHAPTER 3 INTERRUPTS
High-order byte of
the data counter
Initial value
Low-order byte of
the data counter
Initial value
■ I/O Register Address Pointer (IOA)
The I/O register address pointer (IOA) is a 16-bit register that indicates the lower address (A15
to A00) of the I/O register that transfers data to or from the buffer. Because the upper part of
the register address (A23 to A16) is all 0s, the pointer can specify any I/O register between
000000
H
Figure 3.6-5 Structure of the I/O Register Address Pointer (IOA)
High-order byte of the
I/O address pointer
Initial value
Low-order byte of the
I/O address pointer
Initial value
2
■ EI
OS Status Register (ISCS)
2
The EI
(increment or decrement), the format of transferred data (byte or word), and the data transfer
direction between the buffer address pointer and the I/O register address pointer. Also, this
register indicates whether the buffer address pointer and I/O register address pointer has been
updated or left unchanged.
2
EI OS status register (ISCS)
[bit7 to bit5]
Reserved bits. Always set these bits to "0" when setting the ISCS.
74
Figure 3.6-4 Structure of the Data Counter (DCT)
15 14
bit
B15 B14 B13
(X) (X)
7 6
bit
B07 B06
(X) (X)
and 00FFFF .
H
15 14
bit
A15 A14
(X) (X)
7 6
bit
A07 A06
(X) (X)
OS status register (ISCS) is an eight-bit register that indicates an updating mode
Figure 3.6-6 Configuration of EI
7
bit
Reserved Reserved Reserved
Read/write
(-)
Initial value
(X)
13 12 11 10
B12 B11 B10
(X) (X) (X) (X)
5 4 2
3
B05 B04 B03 B02
(X) (X) (X) (X)
13 12 11
A13 A12 A11
(X) (X) (X)
5 4
3
A05 A04 A03
(X) (X) (X)
2
OS Status Register (ISCS)
6 5 4
IF
(-) (-) (R/W) (R/W)
(X) (X) (X)
9
8
B09 B08 DCTH
(X) (X)
1 0
DCTL
B01 B00
(X) (X)
10 9
8
A10 A09 A08
(X) (X) (X)
2 1 0
A02 A01 A00
(X) (X) (X)
2 1 0
3
BW BF DIR
SE
(R/W) (R/W) (R/W)
(X) (X) (X) (X)
IOAH
IOAL