Fujitsu F2MC-16LX Hardware Manual page 110

CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT
[bit6] SLP
Writing "1" in SLP causes a transition to the sleep mode. Writing "0" performs no operation.
When a reset occurs or the sleep or stop mode is released, this bit is cleared to "0".
Simultaneously writing "1" in the STP and SLP bits causes a transition to the watch or stop
mode. This bit is a write only bit. The read value is always "0".
[bit5] SPL
When SPL is "0", the external pin levels are retained in the watch or stop mode. When it is
"1", the external pins are set to high impedance in the watch or stop mode. When a reset
occurs, this bit is cleared to "0". This bit is a read/write bit.
[bit4] RST
Writing "0" in the RST bit generates the internal reset signal for three machine cycles.
Writing "1" performs no operation. When this bit is read, the value is "1".
[bit3] Reserved
Be sure to set this bit to "1".
[bit2, bit1] CG1 and CG0
The CG1 and CG0 bits set the temporary stop cycle count for the intermittent CPU operation
function. When a reset occurs as a result of power-on, hardware standby, or watchdog,
these bits are initialized to "00" but are not initialized by a reset caused by another reset
cause. These bits are read/write bits.
The intermittent CPU operation function stops the clock supplied to the CPU for the specified
time and delays the start of the internal bus cycle in the following case:
- When registers, internal memory, internal peripherals, and the external bus are accessed
Processing can be performed with low-power consumption because the CPU execution
speed is lowered by supplying the internal peripherals with a high-speed clock.
Table 5.2-2 Settings of the Bits for Setting the Clock Temporary Stop Cycle Count
CG1
0
0
1
1
[bit0] Reserved
Be sure to set this bit to "0".
94
(CG1 and CG0)
CG0
0 0 cycle (CPU clock = peripheral clock)
1 9 cycles (CPU clock:periperal clock = 1:about 3 to 4)
0 17 cycles (CPU clock:periperal clock = 1:about 5 to 6)
1 33 cycles (CPU clock:periperal clock = 1:about 9 to 10)
Temporary stop cycle count for the CPU clock