Fujitsu F2MC-16LX Hardware Manual page 257

[bit12 ,bit11] CT1 and CT0 (Compare time)
The CT1 and CT0 bits set the machine cycle number at compare.
Table 15.2-8 CT1 and CT0 (Machine Cycle Number Setting Bits at Compare)
CT1 CT0
0 0
0 1
1 0
1 1
Notes:
• To set these bits at "00", confirm that the machine clock is 8 MHz or slower.
• If the machine clock is faster than 8 MHz, conversion accuracy cannot be guaranteed.
[bit9 to bit0] D9 to D0
D9 to D0 are A/D conversion store registers and digital values of the conversion result are
stored.
Values in this register are updated whenever a conversion is completed. Usually, the last
value of conversion is stored. The registers support the conversion data protection function.
See Section "15.3 Operation of A/D Converter".
These registers are undefined at reset.
Notes:
• Do not write data to this register during A/D operation.
• D9 and D8 are not used in 8-bit mode. Read values of D9 and D8 are undefined.
Machine cycle at compare
176 machine cycle
352 machine cycle
Reserved
Reserved
15.2 Resisters of the A/D Converter
Compare time
22µs/machine clock 8 MHz
22µs/machine clock 16 MHz
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