16-Bit Free-Run Timer Operations - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 10 16-BIT I/O TIMER

10.4 16-Bit Free-Run Timer Operations

The 16-bit free-run timer starts counting from counter value 0000
released. This counter value is used as the reference time of the 16-bit output
compare and the 16-bit input capture operation.
■ 16-bit Free-run Timer Operations
A counter value is cleared under the following conditions:
• An overflow occurs.
• A match occurs with the output compare register 0 value. (Mode setting is required.)
• Value "1" is written in the CLR bit of the TCCS register during operation.
• 0000
• Reset
An interrupt can occur when an overflow occurs or when the counter is cleared by a match with
the compare register 0 value. (The compare match interrupt requires mode setting.)
Counter value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Reset
Interrupt
174
is written in the TCDT register during stop.
H
Figure 10.4-1 Clearing the Counter by an Overflow
after the reset is
H
Overflow
Time