Uart Block Diagram - Fujitsu F2MC-16LX Hardware Manual

17.2 UART Block Diagram

Figure 17.2-1 shows a UART block diagram.
■ UART Block Diagram
Control signal
Communication
prescaler
16-bit
(Internal
reload
connection)
timer 0
External clock
SIN
Receiver state
decision circuit
SMR
register
Figure 17.2-1 UART Block Diagram
Clock
selection
Receiver clock
circuit
Receiver control circuit
Start bit detection
circuit
Received bit
counter
Received parity
counter
Receiver shifter
Receive error signal
2
for EI OS (to CPU)
F
MD1
MD0
CS2
SCR
CS1
register
CS0
SCKE
SOE
Transmitter clock
Transmitter control circuit
End of
reception
SIDR
2
MC-16LX BUS
PEN
P
SBL
SSR
CL
register
A/D
REC
RXE
TXE
17.2 UART Block Diagram
Receiver interrupt
(to CPU)
SCK
Transmitter
interrupt (to CPU)
Transmitter start
circuit
Transmitted bit
counter
Transmitted
parity counter
SOT
Transmitter shifter
Start of
transmission
SODR
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
Control signal
259